
The SOC Timing Engineer role involves ensuring timing closure and signoff for advanced FPGA/SoC designs. Ideal candidates will have a solid background in static timing analysis and experience with EDA tools.
As an SOC Timing Engineer, you will be responsible for achieving timing closure and signoff for FPGA/SoC and subsystem timing. You will engage in static timing analysis, derive interface timing constraints, and perform final timing signoff. Collaboration with design and architecture teams for timing convergence analysis, as well as with the physical design team for timing closure, will be key aspects of your role.
Experience in static timing analysis and industry-standard EDA tools like Primetime/PTPX
Good understanding of timing constraints, clocking, PVT, etc.
Tapeout experience in the latest technology (10nm or lower)
BE/MS/PhD in Electronics/Electrical Engineering with 3+ years' experience in physical design and timing closure/signoff
Strong communication, problem-solving, and analytical skills
Altera has not disclosed the salary for this role.
This SOC Timing Engineer position is based in Penang, Malaysia. This role is fully on-site.
Altera is looking for Experience in static timing analysis and industry-standard EDA tools like Primetime/PTPX; Good understanding of timing constraints, clocking, PVT, etc.; Tapeout experience in the latest technology (10nm or lower).
Apply directly on SuperJobs — create a free profile, upload your CV once and submit. There is no agency fee and no charge to applicants. Applications close 2026-11-07.
Company
Altera
Location
Penang
Salary
Undisclosed
Skills Required
6 skills
Click to submit your application
Altera has not disclosed the salary for this role.
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