Senior Lead Engineer, Hardware Design (FPGA / CPLD) at Celestica Gbs Malaysia Sdn. Bhd. - Undisclosed
Role Summary
The Senior Lead Engineer will lead hardware design projects, focusing on FPGA and CPLD technologies. This role requires collaboration with various teams to deliver high-quality engineering solutions.
Job Description
Celestica Gbs Malaysia Sdn. Bhd. is seeking a Senior Lead Engineer specializing in Hardware Design with a focus on FPGA and CPLD technologies. This role involves leading design projects, collaborating with cross-functional teams, and ensuring high-quality hardware solutions that meet customer requirements. The ideal candidate will have a strong background in thermal engineering and testing within the technology sector.
Job Requirements
Bachelor's degree in Electrical Engineering or related field
Proven experience in hardware design, specifically with FPGA and CPLD
Strong understanding of thermal engineering principles
Ability to work collaboratively in a team environment
Excellent problem-solving skills and attention to detail
Senior Lead Engineer, Hardware Design (FPGA / CPLD) - Frequently Asked Questions
What is the salary for a Senior Lead Engineer, Hardware Design (FPGA / CPLD) at Celestica Gbs Malaysia Sdn. Bhd. in Undisclosed?
Celestica Gbs Malaysia Sdn. Bhd. has not disclosed the salary for this role. Senior Lead Engineer, Hardware Design (FPGA / CPLD) positions in Undisclosed typically pay RM800–RM10,000 per month, based on the 171 comparable vacancies currently listed on SuperJobs.
Where is this Senior Lead Engineer, Hardware Design (FPGA / CPLD) job located?
This Senior Lead Engineer, Hardware Design (FPGA / CPLD) position is based in Undisclosed, Malaysia. This role is fully on-site.
What qualifications do I need for this Senior Lead Engineer, Hardware Design (FPGA / CPLD) role?
Celestica Gbs Malaysia Sdn. Bhd. is looking for Bachelor's degree in Electrical Engineering or related field; Proven experience in hardware design, specifically with FPGA and CPLD; Strong understanding of thermal engineering principles.
How do I apply for this Senior Lead Engineer, Hardware Design (FPGA / CPLD) job at Celestica Gbs Malaysia Sdn. Bhd.?
Apply directly on SuperJobs — create a free profile, upload your CV once and submit. There is no agency fee and no charge to applicants. Applications close 2026-11-08.
Quick Info
Company
Celestica Gbs Malaysia Sdn. Bhd.
Location
Undisclosed
Salary
Undisclosed
Skills Required
7 skills
Click to submit your application
Required Skills
Senior Lead Engineer, Hardware Design (FPGA / CPLD) Salary at Celestica Gbs Malaysia Sdn. Bhd.
Celestica Gbs Malaysia Sdn. Bhd. has not disclosed the salary for this role. Senior Lead Engineer, Hardware Design (FPGA / CPLD) positions in Undisclosed typically pay RM800–RM10,000 per month, based on the 171 comparable vacancies currently listed on SuperJobs.
How to Apply for This Senior Lead Engineer, Hardware Design (FPGA / CPLD) Role
- Click Apply Now and sign in, or create a free SuperJobs profile. It takes about two minutes and there is no agency fee.
- Upload your CV once and answer any screening questions Celestica Gbs Malaysia Sdn. Bhd. asks. Your profile is reused for every application after this one.
- Submit, then track the application and any employer replies from your dashboard. Applications close 2026-11-08, so apply early.
Application Tips
- Ensure your resume highlights relevant skills and experience
- Tailor your application to match the role requirements
- Double-check all information before submitting
- Submit your application as soon as possible to increase your chances
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